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PhD position - field effect nanoionic synaptic transistors for neuromorphic applications
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JOB DETAILS
Published: 1 month ago
Application deadline: Oct 31
Location: Grenoble, France
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PhD position - field effect nanoionic synaptic transistors for neuromorphic applications

SL-DRT-19-0631

RESEARCH FIELD

Electronics and microelectronics - Optoelectronics

ABSTRACT

Neuromorphic computing represents an innovative technology that can perform intelligent and energy-efficient computation, whereas construction of neuromorphic systems requires biorealistic synaptic elements with rich dynamics that can be tuned based on a robust mechanism. As a result, there exists a tremendous upsurge of research interests on building neuromorphic systems, especially by exploiting the scalability and functionality of emerging devices (memristors, Reram). Recently, there is a growing interest on 3-terminal synaptic architectures (memtransistors), whose additional input terminal and modified device configuration have proven favorable for achieving complicated synaptic functions. Today, ion gated transistors appear as one of the most promising candidates, due to their low consumption, scalability and integration. They rely on the use of an ion conductor as a gate dielectric to drive or attract ions to/from the channel. Xxx. In this context, the objective of this PhD is to investigate novel solid-state nanoionic transistors as a synaptic device for neuromorphic applications.The main objective of the PhD is to investigate the potential synaptic behavior that can be achieved in field effect nanoionic transistors. To this aim various materials and device architectures will be characterized: channel with (i) ionic conductor or (ii) ionic conductor/host material bilayer. On these structures, synaptic behavior features will be quantified in terms of: linearity, symmetry, energy consumption etc…modelling could be used to analyze the physical effects taking place in the devices: ion drift and accumulation in the channel bulk or interfaces will be described and simulated. Based on the obtained results, a benchmark among the various tested technologies will be proposed. Then, the link between device stack (materials, thicknesses…) and synaptic capabilities will be clarified. The objective is to propose new device stacks (new elements, multilayers…) to optimize the device performances.

LOCATION

Département Composants Silicium (LETI)

Laboratoire Micro-Batteries Embarquées

Grenoble

CONTACT PERSON

OUKASSI Sami

CEA

DRT/DCOS//LMBE

17 Av. des MartyrsGrenoble

Phone number: 0438782924

Email: sami.oukassi@cea.fr

UNIVERSITY / GRADUATE SCHOOL

Ecole Centrale Paris

Physique et Ingénierie: électrons, photons et sciences du vivant (EOBE)

START DATE

Start date on 01-09-2019

THESIS SUPERVISOR

SCHNEEGANS Olivier

centrale-supelec Paris

LGEP

CNRS UMR8507 - CentraleSupélec - UPSud - UPMCPlateau de Moulon 91192 Gif sur Yvette CedexTél : 01.69.85.16.33 / Fax : 01.69.41.83.18

Phone number: 01.69.85.16.33

Email: olivier.schneegans@lgep.supelec.fr

« The age limit is 26 years for PhD offers and 30 years old for post-doc offers. »

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